Develop UVM/SystemVerilog testbenches for IP and SoC-level verification, including stimulus generation, checkers, and coverage models.
Execute formal verification using tools like JasperGold to prove design correctness and uncover RTL bugs.
Create and debug constrained-random and directed tests to validate power management features (clock gating, voltage scaling).
Analyze coverage metrics (code, functional, assertion) and drive closure to 100% sign-off criteria.
Build Python/Perl scripts to automate verification flows, regression testing, and data analysis.
Support post-silicon debug by replicating hardware issues in simulation and collaborating with cross-functional teams.
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